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this is information on a product in full production. august 2014 docid6512 rev 13 1/46 m950x0-w m950x0-r m950x0-df 4 kbit, 2 kbit and 1 kbit serial spi bus eeprom with high-speed clock datasheet - production data features ? compatible with spi bus serial interface (positive clock spi modes) ? single supply voltage: ? 2.5 v to 5.5 v for m950x0-w ? 1.8 v to 5.5 v for m950x0-r ? 1.7 v to 5.5 v for m95040-df ? high-speed 20 mhz clock rate, 5 ms write time ? memory array: ? 1/2/4 kbit (128/256/512 bytes) of eeprom ? page size: 16 bytes ? write protection by bl ock: 1/4, 1/2 or whole memory ? additional write lockable page (identification page) ? enhanced esd protection ? more than 4 million write cycles ? more than 200-year data retention ? packages rohs-compliant and halogen-free (ecopack?) so8 (mn) 150 mil width tssop8 (dw) 169 mil width ufdfpn8 (mc) 2 x 3 mm table 1. device summary reference part number m950x0-w m95040-w m95020-w m95010-w m950x0-r m95040-r m95020-r m95010-r m950x0-df m95040-df www.st.com
contents m950x0-w m950x0-r m950x0-df 2/46 docid6512 rev 13 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 serial data output (q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 serial data input (d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 serial clock (c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 chip select (s ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 hold (hold ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.6 write protect (w ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.7 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.8 supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.8.1 operating supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.8.2 device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.8.3 power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.8.4 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 connecting to the spi bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 spi modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3 data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 write enable (wren) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.2 write disable (wrdi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3 read status register (rdsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3.1 wip bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3.2 wel bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3.3 bp1, bp0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
docid6512 rev 13 3/46 m950x0-w m950x0-r m950x0-df contents 3 6.4 write status register (wrsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.5 read from memory array (read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.6 write to memory array (write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.7 read identification page (available only in m95040-d device) . . . . . . . . 25 6.8 write identification page (available only in m95040-d device) . . . . . . . . 26 6.9 read lock status (available only in m95040-d device) . . . . . . . . . . . . . . 27 6.10 lock identification page (available only in m95040-d device) . . . . . . . . . 28 7 power-up and delivery states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.1 power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.2 initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 11 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
list of tables m950x0-w m950x0-r m950x0-df 4/46 docid6512 rev 13 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 4. instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 5. significant bits within the address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 6. status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 7. address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 8. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 9. operating conditions (m950x0-w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 table 10. operating conditions (m950x0-r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 11. operating conditions (m95040-df, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 12. ac test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 13. cycling performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 14. memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 15. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 16. dc characteristics (m950x0-w, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 17. dc characteristics (m950x0-r or m95040-df, devi ce grade 6) . . . . . . . . . . . . . . . . . . . . . 34 table 18. ac characteristics (m950x0-w, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 19. ac characteristics (m950x0-r or m95040-df, devi ce grade 6) . . . . . . . . . . . . . . . . . . . . . 36 table 20. ac characteristics (m950x0-w, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 21. ac characteristics (m950x0-r, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 22. so8n 8-lead plastic small outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 23. tssop8 8-lead thin shrink small outline, packa ge mechanical data . . . . . . . . . . . . . . . . . 41 table 24. ufdfpn8 (mlp8) 8-lead ultra thin fine pitch dual flat package no lead 2 3mm, data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 25. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 26. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
docid6512 rev 13 5/46 m950x0-w m950x0-r m950x0-df list of figures 5 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. 8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. bus master and memory devices on the spi bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4. spi modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5. hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 6. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 7. write enable (wren) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 figure 8. write disable (wrdi) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 9. read status register (rdsr) se quence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 10. write status register (wrsr) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 11. read from memory array (read) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 12. byte write (write) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 13. page write (write) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 14. read identification page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 15. write identification page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 16. read lock status sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 17. lock id sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 18. ac test measurement i/o waveform (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 19. serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 20. hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 21. serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 22. so8n 8-lead plastic small outline 150 mils body width, package outline . . . . . . . . . . . . . . 40 figure 23. tssop8 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 24. ufdfpn8 (mlp8) 8-lead ultra thin fine pitch dual flat package no lead 2 3mm, outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
description m950x0-w m950x0-r m950x0-df 6/46 docid6512 rev 13 1 description the m95010/ m95020/m95040 devices (m950x0) are electrically erasable programmable memories (eeproms) organized as 128/256/512 x 8 bits res pectively, accessed through the spi bus. the m950x0-w can operate with a supply voltage from 2.5 v to 5.5 v, the m950x0-r can operate with a supply voltage from 1.8 v to 5.5 v, and the m950x0-df can operate with a supply voltage from 1.7 v to 5.5 v, over an ambient temperature range of -40 c / +85 c. the m950x0-df offers an additional page, na med the identification page (16 bytes). the identification page can be used to store se nsitive application parameters which can be (later) permanently locked in read-only mode. figure 1. logic diagram figure 2. 8-pin package connections 1. see section 10: package mechanical data for package dimensions, and how to identify pin-1. !)# 3 6 ## -xxx (/,$ 6 33 7 1 # $ $ 6 33 # (/,$ 1 36 ## 7 !)$ -xxx
docid6512 rev 13 7/46 m950x0-w m950x0-r m950x0-df description 45 table 2. signal names signal name function c serial clock d serial data input q serial data output s chip select w write protect hold hold v cc supply voltage v ss ground
signal description m950x0-w m950x0-r m950x0-df 8/46 docid6512 rev 13 2 signal description during all operations, v cc must be held stable and within the specified valid range: v cc (min) to v cc (max). all of the input and output signals can be held high or low (according to voltages of v ih , v oh , v il or v ol , as specified in table 16: dc characteristics (m950x0-w, device grade 6) and table 17: dc characteristics (m950x0-r or m95040-df, device grade 6) . these signals are described next. 2.1 serial data output (q) this output signal transfers data serially out of the device. data is sh ifted out on the falling edge of serial clock (c). 2.2 serial data input (d) this input signal transfers data serially into th e device. it receives instructions, addresses, and the data to be written. values are latched on the rising edge of serial clock (c). 2.3 serial clock (c) this input signal provides the timing of the serial interface. instructions, addresses, or data present at serial data input (d) are latched on the rising edge of serial clock (c). data on serial data output (q) changes after the falling edg e of serial clock (c). 2.4 chip select (s ) when this input signal is high, the device is de selected and serial data output (q) is at high impedance. unless an in ternal write cycle is in progress , the device will be in the standby power mode. driving chip select ( s ) low selects the device, plac ing it in the active power mode. after power-up, a falling edge on chip select ( s ) is required prior to the start of any instruction. 2.5 hold (hold ) the hold ( hold ) signal is used to pause any serial communications with the device without deselecting the device. during the hold condition, the serial data output (q) is high impedance, and serial data input (d) and serial clock (c) are don?t care. to start the hold condition, the device must be sele cted, with chip select ( s ) driven low.
docid6512 rev 13 9/46 m950x0-w m950x0-r m950x0-df signal description 45 2.6 write protect (w ) this input signal controls whet her the memory is write prot ected. when write protect ( w ) is held low, writes to the memory are disabl ed, but other operations remain enabled. write protect ( w ) must either be driven high or low, but must not be left floating. 2.7 v ss ground v ss is the reference for the v cc supply voltage. 2.8 supply voltage (v cc ) 2.8.1 operating supply voltage (v cc ) prior to selecting the memory and issuing instructions to it, a valid and stable v cc voltage within the specified [v cc (min), v cc (max)] range must be applied (see table 9: operating conditions (m950x0-w) , table 10: operating conditions (m950x0-r) and table 11: operating conditions (m95040-df, device grade 6) ). this voltage must remain stable and valid until the end of the transmission of the inst ruction and, for a write instruction, until the completion of the internal write cycle (t w ). in order to secure a stable dc supply voltage, it is recommended to decouple the v cc line with a suitable capacitor (usually of the order of 10 nf to 100 nf) close to the v cc /v ss package pins. 2.8.2 device reset in order to prevent inadvertent write operations during power-up, a power-on-reset (por) circuit is included. at power- up, the device does not respon d to any instruction until v cc reaches the internal reset threshold voltage (this threshold is defined in table 9: operating conditions (m950x0-w) , table 10: operating conditions (m950x0-r) and table 11: operating conditions (m95040-df, device grade 6) as v res ). when v cc passes over the por threshold, the device is reset and is in the following state: ? standby power mode ? deselected (note that , to be executed, an instruction must be preceded by a falling edge on chip select (s )) ? status register value: ? write enable latch (wel) is reset to 0 ? write in progress (wip) is reset to 0 ? srwd, bp1 and bp0 bits remain unchanged (non-volatile bits) when the device is in the above stat e, it must not be accessed until v cc reaches a valid and stable v cc voltage within the specified [v cc (min), v cc (max)] range defined in table 9: operating conditions (m950x0-w) , table 10: operating conditions (m950x0-r) and table 11: operating conditions (m95040-df, device grade 6) .
signal description m950x0-w m950x0-r m950x0-df 10/46 docid6512 rev 13 2.8.3 power-up conditions when the power supply is turned on, v cc rises continuously from v ss to v cc . during this time, the chip select ( s ) line is not allowed to float but should follow the v cc voltage. it is therefore recommended to connect the s line to v cc via a suitable pull-up resistor (see figure 3: bus master and memory devices on the spi bus ). in addition, the chip select ( s ) input offers a built-in safety feature, as the s input is edge sensitive as well as level sensitive: after pow er-up, the device does not become selected until a falling edge has first be en detected on chip select ( s ). this ensures that chip select ( s ) must have been high, prior to going low to start the first operation. the v cc voltage has to rise continuously from 0 v up to the minimum v cc operating voltage defined in table 9: operating cond itions (m950x0-w) , table 10: operating conditions (m950x0-r) and table 11: operating conditions (m95040-df, device grade 6) and the rise time must not vary faster than 1 v/s. 2.8.4 power-down during power-down (continuous decrease in the v cc supply voltage below the minimum v cc operating voltage defined in table 9: operating conditions (m950x0-w) , table 10: operating conditions (m950x0-r) and table 11: operating conditions (m95040-df, device grade 6) ), the device must be: ? deselected (chip select s should be allowed to fo llow the voltage applied on v cc ) ? in standby power mode (there should not be any internal write cycle in progress).
docid6512 rev 13 11/46 m950x0-w m950x0-r m950x0-df connecting to the spi bus 45 3 connecting to the spi bus the device is fully compatib le with the spi protocol. all instructions, addresses and input data bytes ar e shifted in to the device, most significant bit first. the serial data input (d) is sampled on the first rising edge of the serial clock (c) after chip select ( s ) goes low. all output data bytes are shifted out of the devi ce, most significant bit first. the serial data output (q) is latched on the first falling edge of the serial clock (c ) after the instruction (such as the read from memory array and read status register instructions) have been clocked into the device. figure 3: bus master and memory devices on the spi bus shows an example of three memory devices connected to an mcu, on an spi bus. only one memory device is selected at a time, so only one memory device drives th e serial data output (q) line at a time, the other memory devices are high impedance. the pull-up resistor r (represented in figure 3: bus master and memory devices on the spi bus ) ensures that a device is not sele cted if the bus master leaves the s line in the high impedance state. in applications where the bus master might ent er a state where all spi bus inputs/outputs would be in high impedance at the same time (f or example, if the bus master is reset during the transmission of an instruction), the clock line (c) must be connected to an external pull- down resistor so that, if all inputs/outputs become high impedance, the c line is pulled low (while the s line is pulled high): this ensures that s and c do not become high at the same time, and so, that the t shch requirement is met. the typical value of r is 100 k .. figure 3. bus master and memory devices on the spi bus 1. the write protect (w ) and hold (hold ) signals should be driven, high or low as appropriate. ai12304b bus master spi memory device sdo sdi sck cqd s spi memory device cqd s spi mmory device cqd s cs3 cs2 cs1 spi interface with (cpol, cpha) = (0, 0) or (1, 1) w hold w hold w hold rrr v cc v cc v cc v cc v ss v ss v ss v ss r
connecting to the spi bus m950x0-w m950x0-r m950x0-df 12/46 docid6512 rev 13 3.1 spi modes the device can be driven by a microcontroller wit h its spi peripheral running in either of the following modes: ? cpol=0, cpha=0 ? cpol=1, cpha=1 for these two modes, input data is latched in on the rising edge of serial clock (c), and output data is available from t he falling edge of serial clock (c). the difference between the two modes, as shown in figure 4: spi modes supported , is the clock polarity when the bus master is in stand-by mode and not transferring data: ? c remains at 0 for (cpol=0, cpha=0) ? c remains at 1 for (cpol=1, cpha=1) figure 4. spi modes supported !)" # -3" #0(! $ #0/, 1 # -3"
docid6512 rev 13 13/46 m950x0-w m950x0-r m950x0-df operating features 45 4 operating features 4.1 hold condition the hold ( hold ) signal is used to pause any serial communications with the device without resetting the clocking sequence. during the hold condition, the serial data output (q) is high impedance, and serial data input (d) and serial clock (c) are don?t care. to enter the hold condition, the device must be selected, with chip select ( s ) low. normally, the device is kept selected, fo r the whole duration of the hold condition. deselecting the device while it is in the hold condition has the effect of resetting the state of the device, and this mechanism can be used if it is required to reset any processes that had been in progress. the hold condition starts when the hold ( hold ) signal is driven low at the same time as serial clock (c) already being low (as shown in figure 5: hold condition activation ). the hold condition ends when the hold ( hold ) signal is driven high at the same time as serial clock (c) already being low. figure 5: hold condition activation also shows what happens if the rising and falling edges are not timed to coincide with serial clock (c) being low. figure 5. hold condition activation 4.2 status register figure 6 shows the position of the status register in the control logic of the device. this register contains a number of control bits and status bits, as shown in table 6: status register format and as detailed in section 6.3: read status register (rdsr) . !)$ (/,$ # (old #ondition (old #ondition
operating features m950x0-w m950x0-r m950x0-df 14/46 docid6512 rev 13 4.3 data protection and protocol control to help protect the device from data corruption in noisy or poorly controlled environments, a number of safety features have been built in to the device. the main security measures can be summarized as follows: ? wel bit is reset at power-up. ? chip select (s ) must rise after the eighth clock count (or multiple thereof) in order to start a non-volatile write cycle (in the me mory array or in the status register). ? accesses to the memory array are ignored du ring the non-volatile programming cycle, and the programming cycl e continues unaffected. ? invalid chip select (s ) and hold (hold ) transitions are ignored. for any instruction to be accepted and executed, chip select ( s ) must be driven high after the rising edge of serial clock (c) that latches the last bit of the instruction, and before the next rising edge of serial clock (c). for this, ?the last bit of the instruction? can be the eighth bit of the instruction code, or the eighth bit of a data byte, depending on the instruction (except in the case of rdsr and read instructions). moreover, the ?next rising edge of clock? might (or might not) be the next bus transaction for some other device on the bus. when a write cycle is in progress, the device protects it against external interruption by ignoring any subsequent read, write or wrsr instruction until the present cycle is complete. table 3. write-protected block size status register bits protected block protected array addresses bp1 bp0 m95040 m95020 m95010 0 0 none none none none 0 1 upper quarter 180h - 1ffh c0h - ffh 60h - 7fh 1 0 upper half 100h - 1ffh 80h - ffh 40h - 7fh 1 1 whole memory 000h - 1ffh 00h - ffh 00h - 7fh
docid6512 rev 13 15/46 m950x0-w m950x0-r m950x0-df memory organization 45 5 memory organization the memory is organized as shown in figure 6 . figure 6. block diagram 069 ,k> ^ t }v??}oo}p] ,]pz}o?p pv??}? /lk?z](??p]??? ????p]??? v}v?? ? ?p]??? ?p y}? z}? y ^]}(?z z}vo? wzkd ? ^??? ?p]??? /v?](]?]}v?p le l?
instructions m950x0-w m950x0-r m950x0-df 16/46 docid6512 rev 13 6 instructions each command is composed of bytes (msbit tran smitted first), initiate d with the instruction byte, as summarized in table 4 . if an invalid instruction is sent (one not contained in table 4 ), the device automatically enters a wait state until deselected. table 4. instruction set instruction description instruction format wren write enable 0000 x110 (1) 1. x = don?t care. wrdi write disable 0000 x100 (1) rdsr read status register 0000 x101 (1) wrsr write status register 0000 x001 (1) read read from memory array 0000 a 8 011 (2) 2. for m95040, a8 = 1 for the upper half of the memory array and 0 for the lower half, while for m95010 and m95020, a8 is don?t care. write write to memory array 0000 a 8 010 (2) rdid (3) 3. available only for the m95040-df device. read identification page 1000 0011 wrid (3) write identification page 1000 0010 rdls (3) reads the identification page lock status. 1000 0011 lid (3) locks the identificat ion page in read- only mode. 1000 0010 table 5. significant bits within the address byte (1)(2) 1. a: significant address bit. 2. x: bit is don?t care. instructions bit b3 of the instruction byte address byte b7 b6 b5 b4 b3 b2 b1 b0 read or write a8/x (3) 3. for m95040, a8 = 1 for the upper half of the memory array and 0 for the lower half, while for m95010 and m95020, a8 is don?t care. a7 a6 a5 a4 a3 a2 a1 a0 rdid or wrid 0 0000a3a2a1a0 rdls or lid 0 10000000
docid6512 rev 13 17/46 m950x0-w m950x0-r m950x0-df instructions 45 6.1 write enable (wren) the write enable latch (wel) bit must be set prior to each write a nd wrsr instruction. the only way to do this is to send a write enable instruction to the device. as shown in figure 7: write enable (wren) sequence , to send this instruction to the device, chip select ( s ) is driven low, and the bits of the instruction byte are shifted in, on serial data input (d). the devi ce then enters a wait state. it waits for a the device to be deselected, by chip select ( s ) being driven high. figure 7. write enable (wren) sequence & ' $,' 6 4 +ljk,pshgdqfh ,qvwuxfwlrq
instructions m950x0-w m950x0-r m950x0-df 18/46 docid6512 rev 13 6.2 write disable (wrdi) one way of resetting the write enable latch (wel) bit is to send a write disable instruction to the device. as shown in figure 8: write disable (wrdi) sequence , to send this instruction to the device, chip select ( s ) is driven low, and the bits of the instruction byte are shifted in, on serial data input (d). the device then enter s a wait state. it waits for a the device to be deselected, by chip select ( s ) being driven high. the write enable latch (wel) bit is reset by any of the following events: ? power-up ? wrdi instruction execution ? wrsr instruction completion ? write instruction completion ? write protect (w ) line being held low. figure 8. write disable (wrdi) sequence & ' $,' 6 4 +ljk,pshgdqfh ,qvwuxfwlrq
docid6512 rev 13 19/46 m950x0-w m950x0-r m950x0-df instructions 45 6.3 read status register (rdsr) the read status register instruction is used to read the status register. as shown in figure 9 , to send this instruction to the device, chip select ( s ) is first driven low. the bits of the instruction byte are then shifted in, on serial data input (d). the current state of the bits in the status register is shif ted out, on serial data out (q). the read cycle is terminated by driv ing chip select ( s ) high. the status register is always r eadable, even if a write or write status register cycle is in progress. during a write status register cycle , the values of the non-volatile bits (bp0, bp1) become available when a new rdsr instru ction is executed, af ter completion of the write cycle. on the other hand, the two read-onl y bits (write enable latch (wel), write in progress (wip)) are dynamically updated during the ongoing write cycle. it is possible to read the status register contents continuously, as described in figure 9 . bits b7, b6, b5 and b4 are always read as 1. the status and control bits of the status register are as follows: 6.3.1 wip bit the write in progress (wip) bit indicates whether the memory is busy with a write or write status register cycle. when set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress. 6.3.2 wel bit the write enable latch (wel) bit indicates the status of the internal write enable latch. when set to 1 the in ternal write enable latch is set, when set to 0 the internal write enable latch is reset and no write or write st atus register instruction is accepted. table 6. status register format b7 b0 1 1 1 1 bp1 bp0 wel wip block protect bits write enable latch bit write in progress bit
instructions m950x0-w m950x0-r m950x0-df 20/46 docid6512 rev 13 6.3.3 bp1, bp0 bits the block protect (bp1, bp0) bits are non-volatile . they define the size of the area to be software protected against write instructions. these bits are written with the write status register (wrsr) instruction. when one or both of the block protect (bp1, bp0) bits is set to 1, the relevant memory area (as defined in table 3: write-protected block size ) becomes protected against write (write) instructions . the block protect (bp1, bp0) bits can be written provided that the hardware protected mode has not been set. figure 9. read status register (rdsr) sequence c d s 2 1 3456789101112131415 instruction 0 ai01444d q 7 6543210 status register out high impedance msb 7 6543210 status register out msb 7
docid6512 rev 13 21/46 m950x0-w m950x0-r m950x0-df instructions 45 6.4 write status register (wrsr) a write status register (wrsr) instruction a llows new values to be written to the status register. before it can be accepted, a write en able (wren) instructio n must previously have been executed. the wrsr instruction is entered by driving chip select ( s ) low, sending the instruction code followed by the data byte on serial data input (d), and driving the chip select ( s ) signal high. chip select ( s ) must be driven high after the rising edge of serial clock (c) that latches in the eighth bit of the data byte, and befo re the next rising edge of serial clock (c). otherwise, the wrsr inst ruction is not executed. driving the chip select ( s ) signal high at a byte boundary of the input data triggers the self- timed write cycle that takes t w to complete (a s specified in table 16: dc characteristics (m950x0-w, device grade 6) to table 19: ac characteristics (m950x0-r or m95040-df, device grade 6) ). the instruction se quence is shown in figure 10: write status register (wrsr) sequence . while the write status register cycle is in progress, the status register may still be read to check the value of the write in progress (wip) bi t: the wip bit is 1 durin g the self-timed write cycle t w , and, 0 when the write cycle is complete. the wel bit (wri te enable latch) is also reset at the end of the write cycle t w . the wrsr instruction allows the user to change the values of the bp1, bp0 bits which define the size of the area that is to be treated as read only, as defined in table 3: write- protected block size . the contents of the bp1, bp0 bits are updated after the completion of the wrsr instruction, including the t w write cycle. the wrsr instruction has no effect on the b7, b6, b5, b4, b1 and b0 bits in the status register which are always read as 0. figure 10. write status register (wrsr) sequence the wrsr instruction is not accepted, and is not executed, under the following conditions: ? if the write enable latch (wel) bit has not been set to 1 (by executing a write enable instruction just before) ? if a write cycle is already in progress ? if the device has not been deselected, by chip select (s ) being driven high, after the eighth bit, b0, of the data byte has been latched in ? if write protect (w ) is low during the wrsr command (instruction, address and data) c d ai01445b s q 2 1 3456789101112131415 high impedance instruction status register in 0 765432 0 1 msb
instructions m950x0-w m950x0-r m950x0-df 22/46 docid6512 rev 13 6.5 read from memory array (read) as shown in figure 11: read from memory array (read) sequence , to send this instruction to the device, chip select ( s ) is first driven low. the bits of the instruction byte and address byte are then shifted in, on serial data inpu t (d). for the m95040, the most significant address bit, a8, is incorporated as bit b3 of the instruction byte, as shown in table 4: instruction set . the address is loaded into an internal address register, and the byte of data at that address is shifted ou t, on serial data output (q). if chip select ( s ) continues to be driven low, an in ternal bit-pointer is automatically incremented at each clock cycle, and the corresponding data bit is shifted out. when the highest address is reached, the addr ess counter rolls over to zero, a llowing the read cycle to be continued indefinitely. the whole memory can, ther efore, be read with a single read instruction. the read cycle is terminated by driving chip select ( s ) high. the rising edge of the chip select ( s ) signal can occur at any time during the cycle. the first byte addressed can be any byte within any page. the instruction is not accepted, and is not execut ed, if a write cycle is currently in progress. figure 11. read from memory array (read) sequence 1. depending on the memory size, as shown in table 7: address range bits , the most significant address bits are don?t care. table 7. address range bits device m95040 m95020 m95010 address bits a8-a0 a7-a0 a6-a0 # $ !)% 3 1 ! ! ! ! ! ! ! ! ! (igh)mpedance $ata/ut )nstruction "yte!ddress
docid6512 rev 13 23/46 m950x0-w m950x0-r m950x0-df instructions 45 6.6 write to memo ry array (write) as shown in figure 12: byte write (write) sequence , to send this instruction to the device, chip select ( s ) is first driven low. the bits of the instruction byte, address byte, and at least one data byte are then shifted in, on serial data input (d). the instruction is terminated by driving chip select ( s ) high at a byte boundary of the input data. the self-timed write cycle, triggered by the rising edge of chip select ( s ), continues for a period t w (as specified in table 16: dc characteristics (m 950x0-w, device grade 6) to table 19: ac characteristics (m950x0-r or m95040-df, device grade 6) ). after this time, the write in progress (wip) bit is reset to 0. in the case of figure 12: byte write (write) sequence , chip select ( s ) is driven high after the eighth bit of the data byte has been latche d in, indicating that the instruction is being used to write a single byte. if, though, chip select ( s ) continues to be driven low, as shown in figure 13: page write (write) sequence , the next byte of input data is shifted in, so that more than a single byte, starting from the given address towards the end of the same page, can be written in a single inter nal write cycle. if chip select ( s ) still continues to be driven low, the next byte of input data is shifted in, and used to overwrite the byte at the start of the current page. the instruction is not accepted, and is not executed, under the following conditions: ? if the write enable latch (wel) bit has not been set to 1 (by executing a write enable instruction just before) ? if a write cycle is already in progress ? if the device has not been deselected, by chip select (s ) being driven high, at a byte boundary (after the rising edge of serial clock (c) that latches the last data bit, and before the next rising edge of serial clock (c) occurs anywhere on the bus) ? if write protect (w ) is low or if the addressed page is in the area protected by the block protect (bp1 and bp0) bits note: the self-timed write cycle t w is internally executed as a sequence of two consecutive events: [erase addressed byte(s)], followed by [program addressed byte(s)]. an erased bit is read as ?0? and a programmed bit is read as ?1?. figure 12. byte write (write) sequence 1. depending on the memory size, as shown in table 7: address range bits , the most significant address bits are don?t care. $,' ^ y ? ? e ? ? ? ? ? e ? ? ? ? e ? ? ? ? ? ?? ?? ,]pz/u?v /v????]}v ????? ?e?? ???
instructions m950x0-w m950x0-r m950x0-df 24/46 docid6512 rev 13 figure 13. page write (write) sequence 1. depending on the memory size, as shown in table 7: address range bits , the most significant address bits are don?t care. # $ 3 )nstruction "yte!ddress $ata"yte # $ !)$ 3 . $ata"yte . . . . . . . $ata"yte. $ata"yte ! ! ! ! ! ! ! ! !
docid6512 rev 13 25/46 m950x0-w m950x0-r m950x0-df instructions 45 6.7 read identification page (avai lable only in m95040-d device) the read identification page ( rdid) instruction is used to read the identification page (additional page of 16 bytes which can be writ ten and later permanently locked in read-only mode). the chip select ( s ) signal is first driven low, the bits of the instruction byte and address bytes are then shifted in (msb fi rst) on serial data input (d). address bit a7 must be 0 and the other address bits are don't care except the lower address bits [a3:a0] (it might be easier to define these bits as 0, as shown in table 5 ). data is then shifted/clocked out (msb first) on serial data output (q). the first byte addressed can be any byte within the identification page. if chip select ( s ) continues to be driven low, the internal address register is automatically incremented and the byte of data at the new address is shifted out. note that there is no roll over feature in the identification page. the address of bytes to read must not exceed the page boundary. the read cycle is terminated by driving chip select ( s ) high. the rising edge of the chip select ( s ) signal can occur at any time when the data bits are shifted out. the instruction is not accepted, and is not execut ed, if a write cycle is currently in progress. figure 14. read identification page sequence # $ -36 3 1 ! ! ! ! ! ! ! ! (igh)mpedance $ata/ut )nstruction "yte!ddress
instructions m950x0-w m950x0-r m950x0-df 26/46 docid6512 rev 13 6.8 write identification page ( available only in m95040-d device) the write identification page (wrid) instructio n is used to write th e identification page (additional page of 16 bytes which can also be permanently locked in read-only mode). the chip select signal ( s ) is first driven low, and then the bits of the instruction byte, address bytes, and at least one data byte are shifted in (msb first) on serial data input (d). address bit a7 must be 0 and the other addr ess bits are don't care except the lower address bits [a3:a0] (it might be easier to define these bits as 0, as shown in table 5 ). the self-timed write cycle starts from the rising edge of chip select ( s ), and continues for a period t w (as specified in chapter 9: dc and ac parameters ). figure 15. write identification page sequence the instruction is discarded, and is not executed if the block protect bits (bp1,bp0) = (1,1) or one of the conditions defined in section 4.3: data protection and protocol control is not satisfied. 069 ^ y ? ? e ? ? ? ??e??? ? e ? ? ? ? ?? ?? ,]pz/u?v /v????]}v ????? ?e?? ???
docid6512 rev 13 27/46 m950x0-w m950x0-r m950x0-df instructions 45 6.9 read lock status (availa ble only in m95040-d device) the read lock status (rdls) instruction is used to read the lock status. to send this instruction to the device, chip select ( s ) first has to be driven low. the bits of the instruction byte and address bytes are then shifted in (msb first) on serial data input (d). address bit a7 must be 1; all other addres s bits are don't care (it might be easier to define these bits as 0, as shown in table 5 ). the lock bit is the lsb (least significant bit) of the byte read on serial data output (q). it is at ?1? when the lock is active and at ?0? when the lock is not active. if chip select ( s ) continues to be driven low, the same data byte is shifted out. the read cycle is terminated by driving chip select ( s ) high. the instruction sequence is shown in figure 16 . the read lock status instruction is not accepted and not executed if a write cycle is currently in progress. figure 16. read lock status sequence # $ -36 3 1 ! ! ! ! ! ! ! ! (igh)mpedance $ata/ut )nstruction "yte!ddress
instructions m950x0-w m950x0-r m950x0-df 28/46 docid6512 rev 13 6.10 lock identification page (available only in m95040-d device) the lock identification page (lid) command is used to permanently lock the identification page in read-only mode. the lid instruction is issued by driving ch ip select (s) low, sending (msb first) the instruction code, the address and a data byte on serial data input (d), and driving chip select (s) high. in the address sent, a7 must be equal to 1. all other address bits are don't care (it might be easier to define these bits as 0, as shown in table 5 ). the data byte sent must be equal to the binary value xxxx xx1x, where x = don't care. the lid instruction is terminated by driving chip select (s) high at a data byte boundary, otherwise, the instruction is not executed. figure 17. lock id sequence driving chip select ( s ) high at a byte boundary of the input data triggers the self-timed write cycle which duration is t w (specified in section 9: dc and ac parameters ). the instruction sequence is shown in figure 17 . the instruction is discarded, and is not executed if the block protect bits (bp1,bp0) = (1,1) or one of the conditions defined in section 4.3: data protection and protocol control is not satisfied. d^???s ^ y ? ?e??? ?e???? ? ?? ? ?? ?? ,]pz]u?v /v????]}v ?r]???? ?e?? ??? ?e ??
docid6512 rev 13 29/46 m950x0-w m950x0-r m950x0-df power-up and delivery states 45 7 power-up and delivery states 7.1 power-up state after power-up, the device is in the following state: ? low power standby power mode ? deselected (after power-up, a falling edge is required on chip select (s ) before any instructions can be started) ? not in hold condition ? write enable latch (wel) is reset to 0 ? write in progress (wip) is reset to 0 the bp1 and bp0 bits of the status register are unchanged from the previous power-down (they are non-volatile bits). 7.2 initial delivery state the device is delivered with: ? the memory array set to all 1s (each byte = ffh) ? status register: bit srwd =0, bp1 =0 and bp0 =0 ? m95040-d only: the identification page bytes values are don?t care.
maximum rating m950x0-w m950x0-r m950x0-df 30/46 docid6512 rev 13 8 maximum rating stressing the device outside the ratings listed in table 8: absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and operation of the device at these, or any other conditions outside those indicat ed in the operating sections of this specification, is not im plied. exposure to absolute maximum rating conditions for extended periods may affe ct device reliability. table 8. absolute maximum ratings symbol parameter min. max. unit t amr ambient operating temperature ?40 130 c t stg storage temperature ?65 150 c t lead lead temperature during soldering see note (1) 1. compliant with jedec standard j-std-020d (for sma ll-body, sn-pb or pb assembly), the st ecopack? 7191395 specification, and the european directive on restrictions on hazardous substances (rohs directive 2011/65/eu of july 2011). c v o output voltage ?0.50 v cc +0.6 v v i input voltage ?0.50 v cc +1.0 v i ol dc output current (q = 0) - 5 ma i ih dc output current (q = 1) - 5 ma v cc supply voltage ?0.50 6.5 v v esd electrostatic pulse (human body model) voltage (2) 2. positive and negative pulses applied on pin pairs, ac cording to the aec-q100-002 (compliant with jedec std jesd22-a114, c1=100pf, r1=1500 , r2=500 ). -4000v
docid6512 rev 13 31/46 m950x0-w m950x0-r m950x0-df dc and ac parameters 45 9 dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. figure 18. ac test me asurement i/o waveform (1) 1. output hi-z is defined as the point where data out is no longer driven. table 9. operating conditions (m950x0-w) symbol parameter min. max. unit v cc supply voltage 2.5 5.5 v t a ambient operating temperat ure (device grade 6) ?40 85 c table 10. operating conditions (m950x0-r) symbol parameter min. max. unit v cc supply voltage 1.8 5.5 v t a ambient operating temperature ?40 85 c table 11. operating conditions (m95040-df, device grade 6) symbol parameter min. max. unit v cc supply voltage 1.7 5.5 v t a ambient operating temperature ?40 85 c table 12. ac test measurement conditions symbol parameter min. max. unit c l load capacitance 30 pf - input rise and fall times - 50 ns - input pulse voltages 0.2v cc to 0.8v cc v - input and output timing reference voltages 0.3v cc to 0.7v cc v dlg 9 && 9 && 9 && 9 && ,qsxwdqg2xwsxw7lplqj 5hihuhqfh/hyhov ,qsxw/hyhov
dc and ac parameters m950x0-w m950x0-r m950x0-df 32/46 docid6512 rev 13 table 13. cycling performance (1) 1. cycling performance for products iden tified by process letter k (previous products were specified with 1 million cycles at 25 c). symbol parameter test conditions min. max. unit ncycle write cycle endurance t a 25 c, v cc (min) < v cc < v cc (max) - 4,000,000 write cycle t a = 85 c, v cc (min) < v cc < v cc (max) - 1,200,000 table 14. memory cell data retention (1) 1. for products identified by process letter k (previous products were specified with a data retention of 40 years at 55c). the data retention behavior is checke d in production, while the 200-year limit is defined from characterization and qualification results. parameter test conditions min. unit data retention t a = 55 c 200 year table 15. capacitance (1) 1. sampled only, not 100% tested, at ta=25 c and a frequency of 5 mhz. symbol parameter test condition min. max. unit c out output capacitance (q) v out = 0 v - 8 pf c in input capacitance (d) v in = 0 v - 8 pf input capacitance (other pins) v in = 0 v - 6 pf
docid6512 rev 13 33/46 m950x0-w m950x0-r m950x0-df dc and ac parameters 45 table 16. dc characteristics (m950x0-w, device grade 6) symbol parameter test conditions in addition to those defined in table 9 min. max. unit i li input leakage current v in = v ss or v cc - 2a i lo output leakage current s = v cc , v out = v ss or v cc - 2a i cc supply current (read) v cc = 2.5 v, f c = 5 mhz, c = 0.1 v cc /0.9 v cc, q = open -2 ma v cc = 2.5 v, f c = 10 mhz, c = 0.1 v cc /0.9 v cc, q = open -2 v cc = 5.5 v, f c = 20 mhz, c = 0.1 v cc /0.9 v cc, q = open -5 (1) 1. only for the devices iden tified by process letter k. i cc0 (2) 2. characterized only, not tested in production. supply current (write) during t w , s = v cc , 2.5 v < v cc < 5.5 v - 5 ma i cc1 supply current (standby) s = v cc , v cc = 5.5 v, v in = v ss or v cc , -3 (3) 3. 2 a for the devices identif ied by process letter g or s. a s = v cc , v cc = 2.5 v, v in = v ss or v cc , -2 (4) 4. 1 a for the devices identifi ed by process letter g or s. v il input low voltage - ?0.45 0.3 v cc v v ih input high voltage - 0.7 v cc v cc +1 v v ol output low voltage i ol = 1.5 ma, v cc = 2.5 v - 0.4 v v oh output high voltage v cc = 2.5 v and i oh = 0.4 ma or v cc = 5 v and i oh = 2 ma 0.8 v cc -v v res (2) internal reset threshold voltage -1.0 (5) 5. 0.5 v with the device identified by process letter k. 1.65 (6) 6. 1.5 v with the device identified by process letter k. v
dc and ac parameters m950x0-w m950x0-r m950x0-df 34/46 docid6512 rev 13 table 17. dc characteristics (m950x0-r or m95040-df, device grade 6) symbol parameter test conditions in addition to those defined in table 10 or table 11 and table 12 (1) min. max. unit i li input leakage current v in = v ss or v cc - 2a i lo output leakage current s = v cc , voltage applied on q = v ss or v cc - 2a i cc supply current (read) v cc = 1.8 v or 1.7 v, f c = 5 mhz, c = 0.1 v cc /0.9 v cc , q = open -2ma i cc0 (2) supply current (write) v cc = 1.8 v or 1.7 v, during t w , s = v cc -5ma i cc1 supply current (standby) v cc = 1.8 v or 1.7 v, s = v cc , v in = v ss or v cc -1a v il input low voltage v cc < 2.5 v ?0.45 0.25 v cc v v ih input high voltage v cc < 2.5 v 0.75 v cc v cc +1 v v ol output low voltage i ol = 0.15 ma, v cc = 1.8 v or 1.7 v - 0.3 v v oh output high voltage i oh = ?0.1 ma, v cc = 1.8 v or 1.7 v 0.8 v cc -v v res (2) internal reset threshold voltage -1.0 (3) 1.65 (4) v 1. if the application uses the m950x0-r or m95040-df devices with 2.5 v v cc 5.5 v and -40 c t a +85 c, please refer to table 16: dc characteristics (m950x0-w, device grade 6) , rather than to the above table. 2. characterized only, not tested in production. 3. 0.5 v with the device identified by process letter k. 4. 1.5 v with the device identified by process letter k.
docid6512 rev 13 35/46 m950x0-w m950x0-r m950x0-df dc and ac parameters 45 table 18. ac characteristics (m950x0-w, device grade 6) (1) test conditions specified in table 9 and table 12 symbol alt. parameter v cc = 2.5 to 5.5 v (2) v cc = 4.5 to 5.5 v unit min. max. min. max. f c f sck clock frequency d.c. 10 d.c. 20 mhz t slch t css1 s active setup time 30 - 15 - ns t shch t css2 s not active setup time 30 - 15 - ns t shsl t cs s deselect time 40 - 20 - ns t chsh t csh s active hold time 30 - 15 - ns t chsl -s not active hold time 30 - 15 - ns t ch (3) t clh clock high time 40 - 20 - ns t cl (3) t cll clock low time 40 - 20 - ns t clch (4) t rc clock rise time - 2 - 2 s t chcl (4) t fc clock fall time - 2 - 2 s t dvch t dsu data in setup time 10 - 5 - ns t chdx t dh data in hold time 10 - 10 - ns t hhch - clock low hold time after hold not active 30 - 15 - ns t hlch - clock low hold time after hold active 30 - 15 - ns t clhl - clock low set-up time before hold active 0 - 0 - ns t clhh - clock low set-up time before hold not active 0 - 0 ns t shqz (4) t dis output disable time - 40 - 20 ns t clqv (5) t v clock low to output valid - 40 - 20 ns t clqx t ho output hold time 0 - 0 - ns t qlqh (4) t ro output rise time - 40 - 20 ns t qhql (4) t fo output fall time - 40 - 20 ns t hhqv t lz hold high to output valid - 40 - 20 ns t hlqz (4) t hz hold low to output high-z - 40 - 20 ns t w t wc write time - 5 - 5 ms 1. the timing values described in this table are recommended for new designs. 2. only for devices identi fied by process letter k. 3. t ch + t cl must never be lower than the s hortest possible clock period, 1/f c (max). 4. characterized only, not tested in production. 5. t clqv must be compatible with t cl (clock low time): if the spi bus master offers a read setup time t su = 0 ns, t cl can be equal to (or greater than) t clqv ; in all other cases, t cl must be equal to (or greater than) t clqv +t su .
dc and ac parameters m950x0-w m950x0-r m950x0-df 36/46 docid6512 rev 13 table 19. ac characteristics (m950x0-r or m95040-df, device grade 6) (1) 1. the timing values described in this table are recommended for new designs. test conditions specified in table 10 or table 11 and table 12 (2) 2. if the application uses the m950x0- r or m95040-df devices at 2.5 v v cc 5.5 v and -40 c t a +85 c, please refer to table 18: ac characteristics (m950x0-w, device grade 6) , rather than to the above table. symbol alt. parameter min. max. unit f c f sck clock frequency d.c. 5 mhz t slch t css1 s active setup time 60 - ns t shch t css2 s not active setup time 60 - ns t shsl t cs s deselect time 90 - ns t chsh t csh s active hold time 60 - ns t chsl -s not active hold time 60 - ns t ch (3) 3. t ch + t cl must never be lower than the s hortest possible clock period, 1/f c (max). t clh clock high time 80 - ns t cl (3) t cll clock low time 80 - ns t clch (4) 4. characterized only, not tested in production. t rc clock rise time - 2 s t chcl (4) t fc clock fall time - 2 s t dvch t dsu data in setup time 20 - ns t chdx t dh data in hold time 20 - ns t hhch - clock low hold time after hold not active 60 - ns t hlch - clock low hold time after hold active 60 - ns t clhl - clock low set-up time before hold active 0 - ns t clhh - clock low set-up time before hold not active 0 - ns t shqz (4) t dis output disable time - 80 ns t clqv t v clock low to output valid - 80 ns t clqx t ho output hold time 0 - ns t qlqh (4) t ro output rise time - 80 ns t qhql (4) t fo output fall time - 80 ns t hhqv t lz hold high to output valid - 80 ns t hlqz (4) t hz hold low to output high-z - 80 ns t w t wc write time - 5 ms
docid6512 rev 13 37/46 m950x0-w m950x0-r m950x0-df dc and ac parameters 45 table 20. ac characteristics (m950x0-w, device grade 6) (1) 1. not recommended for new designs, for new designs refer to table 18: ac characteristics (m950x0-w, device grade 6) test conditions specified in table 9 and table 12 symbol alt. parameter min. max. unit f c f sck clock frequency d.c. 10 mhz t slch t css1 s active setup time 15 - ns t shch t css2 s not active setup time 15 - ns t shsl t cs s deselect time 40 - ns t chsh t csh s active hold time 25 - ns t chsl -s not active hold time 15 - ns t ch (2) 2. t ch + t cl must never be less than the shor test possible clock period, 1 / f c (max) t clh clock high time 40 - ns t cl (2) t cll clock low time 40 - ns t clch (3) 3. value guaranteed by characterization, not 100% tested in production. t rc clock rise time - 1 s t chcl (3) t fc clock fall time - 1 s t dvch t dsu data in setup time 15 - ns t chdx t dh data in hold time 15 - ns t hhch - clock low hold time after hold not active 15 - ns t hlch - clock low hold time after hold active 20 - ns t clhl - clock low setup time before hold active 0 - ns t clhh - clock low setup time before hold not active 0 - ns t shqz (3) t dis output disable time - 25 ns t clqv t v clock low to output valid - 35 ns t clqx t ho output hold time 0 - ns t qlqh (3) t ro output rise time - 20 ns t qhql (3) t fo output fall time - 20 ns t hhqv t lz hold high to output valid - 25 ns t hlqz (3) t hz hold low to output high-z - 35 ns t w t wc write time - 5 ms
dc and ac parameters m950x0-w m950x0-r m950x0-df 38/46 docid6512 rev 13 table 21. ac characteristics (m950x0-r, device grade 6) (1) 1. not recommended for new designs, for new designs refer to table 19: ac characteristics (m950x0-r or m95040-df, device grade 6) test conditions specified in table 10 and table 12 (2) 2. the test flow guarantees the ac parameter values defined in this table (when v cc = 1.8 v) and the ac parameter values defined in table 20: ac characterist ics (m950x0-w, device grade 6) (when v cc = 2.5 or when v cc = 5.0 v). symbol alt. parameter min. max. unit f c f sck clock frequency d.c. 5 mhz t slch t css1 s active setup time 90 - ns t shch t css2 s not active setup time 90 - ns t shsl t cs s deselect time 100 - ns t chsh t csh s active hold time 90 - ns t chsl -s not active hold time 90 - ns t ch (3) 3. t ch + t cl must never be less than the shor test possible clock period, 1 / f c (max) t clh clock high time 90 - ns t cl (2) t cll clock low time 90 - ns t clch (4) 4. value guaranteed by characteriza tion, not 100% tested in production. t rc clock rise time - 1 s t chcl (3) t fc clock fall time - 1 s t dvch t dsu data in setup time 20 - ns t chdx t dh data in hold time 30 - ns t hhch - clock low hold time after hold not active 70 - ns t hlch - clock low hold time after hold active 40 - ns t clhl - clock low setup time before hold active 0 - ns t clhh - clock low setup time before hold not active 0 - ns t shqz (3) t dis output disable time - 100 ns t clqv t v clock low to output valid - 80 ns t clqx t ho output hold time 0 - ns t qlqh (3) t ro output rise time - 50 ns t qhql (3) t fo output fall time - 50 ns t hhqv t lz hold high to output valid - 50 ns t hlqz (3) t hz hold low to output high-z - 100 ns t w t wc write time - 5 ms
docid6512 rev 13 39/46 m950x0-w m950x0-r m950x0-df dc and ac parameters 45 figure 19. serial input timing figure 20. hold timing figure 21. serial output timing # $ !)d 3 -3"). 1 t$6#( (ighimpedance ,3"). t3,#( t#($8 t#,#( t3(#( t3(3, t#(3( t#(3, t#( t#, t#(#, # 1 !)c 3 1 t#,(, t(,#( t((#( t#,(( t((16 t(,1: # 1 !)f 3 $ !$$2 ,3"). t3(1: t#( t#, t1,1( t1(1, t#(#, t#,18 t#,16 t3(3, t#,#(
package mechanical data m950x0-w m950x0-r m950x0-df 40/46 docid6512 rev 13 10 package mechanical data in order to meet environmental requirements, st offers the device in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. figure 22. so8n 8-lead plastic small outline 150 mils body width, package outline 1. drawing is not to scale. table 22. so8n 8-lead plastic small outline, 150 mils body width, package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. typ. min. max. typ. min. max. a - - 1.75 - - 0.0689 a1 - 0.1 0.25 - 0.0039 0.0098 a2 - 1.25 - - 0.0492 - b - 0.28 0.48 - 0.011 0.0189 c - 0.17 0.23 - 0.0067 0.0091 ccc - - 0.1 - - 0.0039 d 4.9 4.8 5 0.1929 0.189 0.1969 e 6 5.8 6.2 0.2362 0.2283 0.2441 e1 3.9 3.8 4 0.1535 0.1496 0.1575 e 1.27 - - 0.05 - - h - 0.25 0.5 - 0.0098 0.0197 k-08-08 l - 0.4 1.27 - 0.0157 0.05 l1 1.04 - - 0.0409 - - 62$ ( fff e h $ ' f ( k[? $ n pp / / $ *$8*(3/$1(
docid6512 rev 13 41/46 m950x0-w m950x0-r m950x0-df package mechanical data 45 figure 23. tssop8 8-lead thin shri nk small outline, package outline 1. drawing is not to scale. table 23. tssop8 8-lead thin shrink small outline , package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. typ. min. max. typ. min. max. a - - 1.2 - - 0.0472 a1 - 0.05 0.15 - 0.002 0.0059 a2 1 0.8 1.05 0.0394 0.0315 0.0413 b - 0.19 0.3 - 0.0075 0.0118 c - 0.09 0.2 - 0.0035 0.0079 cp - - 0.1 - - 0.0039 d 3 2.9 3.1 0.1181 0.1142 0.122 e 0.65 - - 0.0256 - - e 6.4 6.2 6.6 0.252 0.2441 0.2598 e1 4.4 4.3 4.5 0.1732 0.1693 0.1772 l 0.6 0.45 0.75 0.0236 0.0177 0.0295 l1 1 - - 0.0394 - - -08-08 n (number of leads) 8 8 76623$0 &3 f / ( ( ' $ $ d h e $ /
package mechanical data m950x0-w m950x0-r m950x0-df 42/46 docid6512 rev 13 figure 24. ufdfpn8 (mlp8) 8-lead ultra thin fine pitch dual flat package no lead 2 3mm, outline 1. drawing is not to scale. 2. the central pad (area e2 by d2 in the above illustration) is pulled, internally, to v ss . it must not be allowed to be connected to any other voltage or signal line on the pcb, for example during the soldering process. 3. the circle in the top view of the package indicates the position of pin 1. table 24. ufdfpn8 (mlp8) 8-lead ultra thin fine pitch dual flat package no lead 2 3mm, data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. typ. min. max. typ. min. max. a 0.550 0.450 0.600 0.0217 0.0177 0.0236 a1 0.020 0.000 0.050 0.0008 0.0000 0.0020 b 0.250 0.200 0.300 0.0098 0.0079 0.0118 d 2.000 1.900 2.100 0.0787 0.0748 0.0827 d2 (rev mc) - 1.200 1.600 - 0.0472 0.0630 e 3.000 2.900 3.100 0.1181 0.1142 0.1220 e2 (rev mc) - 1.200 1.600 - 0.0472 0.0630 e 0.500 - - 0.0197 - - k (rev mc) - 0.300 - - 0.0118 - l - 0.300 0.500 - 0.0118 0.0197 l1 - - 0.150 - - 0.0059 l3 - 0.300 - - 0.0118 - eee (2) 2. applied for exposed die paddle and terminals. exclude embedding part of exposed die paddle from measuring. - 0.080 - - 0.0031 - $ % :7?-%e6 ! ! eee , e b $ , % , 0in +
docid6512 rev 13 43/46 m950x0-w m950x0-r m950x0-df part numbering 45 11 part numbering table 25. ordering information scheme example: m95040-d ? w mn 6 t p device type m95 = spi serial access eeprom device function 040 = 4 kbit (512 x 8) 040-d = 4 kbit (512 x 8) plus identification page 020 = 2 kbit (256 x 8) 010 = 1 kbit (128 x 8) operating voltage w = v cc = 2.5 to 5.5 v r = v cc = 1.8 to 5.5 v f = v cc = 1.7 to 5.5 v package mn = so8 (150 mil width) dw = tssop8 (169 mil width) mc = ufdfpn8 (mlp8) 2 3mm device grade 6 = industrial temperature range, ?40 to 85 c. device tested with standard test flow option t = tape and reel packing blank = tube packing plating technology p or g = ecopack ? (rohs compliant)
revision history m950x0-w m950x0-r m950x0-df 44/46 docid6512 rev 13 12 revision history table 26. document revision history date version changes 02-feb-2012 10 document renamed from ?m95040 m95020 m95010? to ?m950x0 m950x0-w m950x0-r? silhouette of udfpn8 (mb or mc) on the cover page updated. section 6.3: read status register (rdsr) updated. text modified in section 6.3.1: wip bit . table 8: absolute maximum ratings updated. figure 24: ufdfpn8 (mlp8) 8-lead ultra thin fine pitch dual flat package no lead 2 3mm, outline modified. table 24: ufdfpn8 (mlp8) 8-lead ultra thin fine pitch dual flat package no lead 2 3mm, data updated. removed tables of available products from section 11: part numbering . 24-may-2013 11 document renamed from ?m95040 m95020 m95010? to ?m950x0-w m950x0-r?. silhouette of udfpn8 (mb or mc) on the cover page updated. section 6.3: read status register (rdsr) updated. text modified in section 6.3.1: wip bit . table 8 and table 24 updated. tables 8, 13, 15, 17, 19 removed. figure 24 modified. removed tables of available products from section 11: part numbering .
docid6512 rev 13 45/46 m950x0-w m950x0-r m950x0-df revision history 45 17-oct-2013 12 added ?m95040-df? part number. updated: ? features : single supply voltage, high-speed clock frequency, memory array, write cycles and data retention ? section 1: description ? figure 6: block diagram ? section 6: instructions : updated introduction and added section 6.7 to section 6.10 ? section 7.2: initial delivery state ? note (1) under table 8: absolute maximum ratings . ? table 16: dc characteristics (m950x0-w, device grade 6) , table 18: ac characteristics (m950x0-w, device grade 6) and table 25: ordering information scheme added table 13: cycling performance , table 14: memory cell data retention , table 17: dc characteristics (m950x0-r or m95040-df, device grade 6) and table 19: ac characteristics (m950x0-r or m95040-df, device grade 6) . renamed table 20 and table 21 . 28-aug-2014 13 updated footnotes: ? 1 in table 13: cycling performance ; ? 1 in table 14: memory cell data retention ; ? 2 in table 19: ac characteristics (m950x0-r or m95040-df, device grade 6) ; ? 2 in table 21: ac characteristics (m950x0-r, device grade 6) . updated table 20 with new title ac characteristics (m950x0-w, device grade 6) and addition of footnote 1 . updated table 21 with new title ac characteristics (m950x0-r, device grade 6) and addition of footnote 1 . updated table 25: ordering information scheme . table 26. document revision history (continued) date version changes
m950x0-w m950x0-r m950x0-df 46/46 docid6512 rev 13 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics ? all rights reserved

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